Index: modules/arch/x86/x86id.c
===================================================================
--- modules/arch/x86/x86id.c	(revision 1610)
+++ modules/arch/x86/x86id.c	(working copy)
@@ -1948,6 +1948,25 @@
       {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_Any|OPA_EA, 0} }
 };
 
+/* SSE4 instructions */
+static const x86_insn_info sse4_insn[] = {
+    { CPU_SSE4, MOD_Op2Add, 0, 0, 0, 3, {0x0F, 0x38, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0}
+    },
+    { CPU_SSE4, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0}
+    }
+};
+
+static const x86_insn_info palignr_insn[] = {
+    { CPU_SSE4, MOD_Op2Add, 0, 0, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3,
+      {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm}
+    },
+    { CPU_SSE4, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm}
+    }
+};
+
 /* AMD 3DNow! instructions */
 static const x86_insn_info now3d_insn[] = {
     { CPU_3DNow, MOD_Imm8, 0, 0, 0, 2, {0x0F, 0x0F, 0}, 0, 2,
Index: modules/arch/x86/x86parse.gap
===================================================================
--- modules/arch/x86/x86parse.gap	(revision 1610)
+++ modules/arch/x86/x86parse.gap	(working copy)
@@ -716,6 +716,23 @@
 INSN	-	movshdup NONE	ssess	0xF316		CPU_SSE3
 INSN	-	movsldup NONE	ssess	0xF312		CPU_SSE3
 INSN	-	mwait	NONE	threebyte   0x0F01C9	CPU_SSE3
+# SSE4 / TNI Tejas New Intructions instructions
+INSN	-	pshufb	NONE	sse4	0x00	CPU_SSE4
+INSN	-	phaddw	NONE	sse4	0x01	CPU_SSE4
+INSN	-	phaddd	NONE	sse4	0x02	CPU_SSE4
+INSN	-	phaddsw	NONE	sse4	0x03	CPU_SSE4
+INSN	-	pmaddubsw	NONE	sse4	0x04	CPU_SSE4
+INSN	-	phsubw	NONE	sse4	0x05	CPU_SSE4
+INSN	-	phsubd	NONE	sse4	0x06	CPU_SSE4
+INSN	-	phsubsw	NONE	sse4	0x07	CPU_SSE4
+INSN	-	psignb	NONE	sse4	0x08	CPU_SSE4
+INSN	-	psignw	NONE	sse4	0x09	CPU_SSE4
+INSN	-	psignd	NONE	sse4	0x0A	CPU_SSE4
+INSN	-	pmulhrsw	NONE	sse4	0x0B	CPU_SSE4
+INSN	-	pabsb	NONE	sse4	0x1C	CPU_SSE4
+INSN	-	pabsw	NONE	sse4	0x1D	CPU_SSE4
+INSN	-	pabsd	NONE	sse4	0x1E	CPU_SSE4
+INSN	-	palignr	NONE	palignr	0x0F	CPU_SSE4
 # AMD 3DNow! instructions
 INSN	-	prefetch NONE	twobytemem  0x000F0D	CPU_3DNow
 INSN	-	prefetchw NONE	twobytemem  0x010F0D	CPU_3DNow
@@ -888,6 +905,10 @@
 			CPU_K6|CPU_Athlon|CPU_Hammer|CPU_EM64T|CPU_FPU|CPU_MMX|\
 			CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_3DNow|CPU_SMM|\
 			CPU_Prot|CPU_Priv
+CPU		conroe	CPU_186|CPU_286|CPU_386|CPU_486|CPU_586|CPU_686|\
+			CPU_EM64T|CPU_FPU|CPU_MMX|\
+			CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSE4|CPU_SMM|\
+			CPU_Prot|CPU_Priv
 
 # Features have "no" versions to disable them, and only set/reset the
 # specific feature being changed.  All other bits are left alone.
@@ -909,6 +930,7 @@
 CPU_FEATURE	svm	CPU_SVM
 CPU_FEATURE	padlock	CPU_PadLock
 CPU_FEATURE	em64t	CPU_EM64T
+CPU_FEATURE	sse4	CPU_SSE4
 
 
 # TARGETMOD parameters:
Index: modules/arch/x86/x86arch.h
===================================================================
--- modules/arch/x86/x86arch.h	(revision 1610)
+++ modules/arch/x86/x86arch.h	(working copy)
@@ -58,6 +58,7 @@
 #define CPU_SVM	    (1UL<<25)	/* Secure Virtual Machine instruction */
 #define CPU_PadLock (1UL<<25)	/* VIA PadLock instruction */
 #define CPU_EM64T   (1UL<<26)	/* Intel EM64T or better */
+#define CPU_SSE4    (1UL<<28)   /* Streaming SIMD extensions 4 required */
 
 /* Technically not CPU capabilities, they do affect what instructions are
  * available.  These are tested against BITS==64.